Periodic digital signals are commonly used in a variety of electronic devices, such as memory devices. Probably the most common of periodic digital signals are clock signals that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock or data strobe signal.
As the speed of memory devices and other devices continue to increase, the “eye” or period in which a digital signal, such as a data signal, is valid becomes smaller and smaller, thus making the timing of a strobe signal or other clock signal used to capture the digital signal even more critical. In particular, as the size of the eye becomes smaller, the propagation delay of the strobe signal can be different from the propagation delay of the captured digital signal(s). As a result, the skew of the strobe signal relative to the digital signal can increase to the point where a transition of the strobe signal is no longer within the eye of the captured signal.
One technique that has been used to ensure the correct timing of a strobe signal relative to captured digital signals is to use a locked loop, such as a delay-lock loop (“DLL”), to generate the strobe signal in particular, a delay-lock loop allows the timing of the strobe signal to be adjusted to minimize the phase error between the strobe signal and the valid eye of the digital signal. A typical delay-lock loop uses a delay line (not shown) consisting of a large number of delay stages. A reference clock signal is applied to the delay line, and it propagates through the delay line to the final delay stage, which outputs a delayed clock signal. The phase of the delayed clock signal is compared to the phase of the reference clock signal to generate a phase error signal. The phase error signal is used to adjust the delay provided by the delay stages in the delay line until the phase of the delayed clock signal is equal to the phase of the reference clock signal.
Another problem associated with the high operating speed of memory and other devices is excessive power consumption, particularly for portable electronic devices like notebook or other portable computers. A significant amount of power consumption in portable computers is the result of power consumed by DRAM devices, which are normally used as system memory. It is therefore important to minimize the power consumed by DRAM devices so that such computers can be powered by batteries over an extended period. Excessive power consumption can also create problems even where DRAM devices are not powered by batteries. For example, the heat generated by excessive power consumption can damage the DRAM devices, and it can be difficult and/or expensive to maintain the temperature of electronic equipment containing the DRAM devices at an acceptably low value.
Power is consumed each time a digital circuit is switched to change the logic level of a digital signal. The rate at which power is consumed by DRAM and other memory devices therefore increases with both the operating speed of such devices and the number of circuits being switched. Thus, the demands for ever increasing operating speeds and memory capacity are inconsistent with the demands for ever decreasing memory power consumption.
Various circuits in DRAM devices consume power at various rates. A significant amount of power is consumed by locked loops, particularly delay-lock loops, which, as explained above are commonly used in DRAM devices. Delay-lock loops consume a great deal of power because the delay lines used in such loops often contain a large number of delay stages, all of which are switched as a reference clock signal propagates through the delay line. The higher reference clock signal frequencies need to operate the DRAM devices at higher speed causes these large number delay stages to be switched at a rapid rate, thereby consuming power at a rapid rate.
A number of techniques have been used to reduce power consumption in DRAM devices while allowing for increases in operating speeds and memory capacity. One approach has been to prevent digital circuits from switching when such circuits are not active since, as mentioned above, power is consumed each time a component in the digital circuit is switched from one state to another. While this approach can significantly reduce the power consumed by DRAM devices, there are circuits in DRAM devices that cannot be rendered inactive without compromising the speed and/or operability of the DRAM devices. Delay-lock loops, for example, often cannot be switched off because of the amount of time needed for the loops to achieve a locked condition after they have been powered down for a considerable period. For these reasons, the coupling of a reference clock signals to delay-lock loops have traditionally been terminated to reduce power consumption only when there is some assurance that it will not be necessary for the DRAM device to read or write data for a considerable period. For example, DRAM devices have been placed in a power-down state when the DRAM device switches to a self-refresh mode or when a computer system containing the DRAM devices switches to a low power standby mode. However, there are other times where the clock signals produced by delay-lock loops are not actually needed, and additional power savings could be achieved. Furthermore, removing the reference clock signals from delay-lock loops for long periods even during extended periods like self-refresh allows the delay of the delay lines used in the delay-lock loops to change considerably, thus requiring an undesirably long period for the delay-lock loop to again achieve a locked condition.
There is therefore a need for a method and system for allowing a reference clock signal to be removed from delay-lock loops to a greater extent, thereby further reducing power consumption, without sacrificing operating speed or performance resulting from the time needed for the loop to achieve a locked condition.